The present invention relates generally to electronic device packaging. More particularly, the present invention relates to ball grid array interconnect design.
Electronic chips are often mounted in ball grid array (xe2x80x9cBGAxe2x80x9d) packages that can be easily attached to a printed circuit board (xe2x80x9cPCBxe2x80x9d) or an electronic component. A typical BGA package includes an electronic chip that is physically and electronically connected to a BGA substrate, which includes an interconnect arrangement that provides conductive paths between points on its chip-mounting surface and corresponding solder balls located on its board-mounting surface. BGA packages are often utilized for high speed electronic devices, e.g., circuits that handle input and/or output signals having data rates of up to 40 Gbps.
In high speed BGA applications, the high speed signals are routed to the perimeter of the BGA ball matrix to provide easy access to the high speed signals (from the perspective of the PCB designer). In this regard, lateral conductive traces must be formed on the BGA substrate to carry the high speed signals from the electronic chip to the perimeter of the BGA substrate; the lateral traces are necessary because the electronic chip is smaller than the BGA substrate. The transition from the lateral trace to the BGA via results in impedance mismatching, high insertion loss, and high reflection loss. In addition, the propagation of high speed signals on the lateral traces can lead to cross talk to adjacent signals and interconnect planes.
An electronic device packaging technique according to the present invention improves the integrity of high speed signals carried by a BGA substrate. A BGA package configured in accordance with the present invention need not employ high speed lateral conductive traces from the electronic device to the perimeter of the BGA solder bump matrix. As a result, the signal paths for critical high speed input/output signals exhibit better impedance matching and lower insertion and reflection losses.
The above and other aspects of the present invention may be carried out in one form by an interconnect substrate for an electronic device. The interconnect substrate includes a device-mounting surface configured to receive an electronic device, a high speed input/output signal contact pad on the device-mounting surface, a component-mounting surface opposite the device-mounting surface, a number of peripheral conductive attachment elements on the component-mounting surface, a number of interior conductive attachment elements bordered by the peripheral conductive attachment elements, and an interconnect via having a first end directly connected to the high speed input/output signal contact pad and having a second end directly connected to one of the interior conductive attachment elements.